Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices. As the devices become more portable, power consumption and speed of components within a computing device become important factors in design considerations.
In some memory architectures, power savings can be achieved during consecutive write operations by controlling the timing of the operation of on-die termination (ODT) circuitry by distributing a control signal, for example, through a signal tree, to the ODT circuitry associated with the input/output (I/O) nodes of a memory during write operations. Although this approach may result in decreased power consumption, as well as savings in surface area, timing accuracy may be sacrificed. As memory architecture become faster, timing tolerances become tighter to a point where the reduced timing accuracy resulting from distributing the control signal to the ODT circuitry through a signal tree becomes insufficient. The timing of the operation of ODT circuitry may be controlled more accurately by using I/O latches located more closely to the ODT circuitry associated with the I/O nodes, however, this may result in increased power consumption.